The present invention relates to electronic circuits, and more particularly to high-speed TTL drivers.
Transistor-transistor logic, commonly referred to as TTL logic, is widely known. A TTL logic circuit is typically driven by a TTL driver circuit adapted to supply a voltage that may vary from 0.8 (VOL, output low maximum) to 2 (VOH, output high minimum) volts. One type of TTL driver circuit (hereinafter alternatively referred to as TTL driver) uses series-connected P-channel MOS (PMOS) and N-channel MOS (NMOS) transistors at its output stage. The PMOS transistor is adapted to supply the high logic voltage level, and the NMOS transistor is adapted to supply the low logic voltage level. The smaller the time period during which both the PMOS and the NMOS transistors are on, the smaller the current consumption. Therefore, ideally the PMOS and NMOS transistors should not be on at the same time.
Conventional TTL drivers include a feed-back circuitry adapted to minimize the overlapping on states of the PMOS and NMOS transistors. FIG. 1 is a transistor schematic diagram of a prior art TTL driver 100. TTL driver 100 includes output stage 120 and control logic 130. Output stage 120 includes PMOS transistor 102 and NMOS transistor 104. Control logic 130 includes inverters 106, 108, 122, 124, NAND gate 110, NOR gate 112, and resistors 114, and 116. As seen from FIG. 1, TTL driver 100 includes a feedback circuitry that feeds the voltage applied to the gate terminal of NMOS transistor 104 to the gate terminal of PMOS Transistors 102 via NAND gate 110, and feeds the voltage applied to the gate terminal of PMOS transistor 102 to the gate terminal of NMOS transistor 104 via NOR gate 112.
When the voltage signal applied to node Vin goes high, the voltage at node A goes high, causing the voltage at node C to go low, thereby causing NMOS transistor 104 to turn off. The low voltage at node C causes the voltage at node D to go high, thereby causing the voltage at node B to go low, which in turn, turns on PMOS transistor 102. Conversely, when the voltage signal applied to node Vin goes low, the voltage at node A goes low, causing the voltage at node B to go high, thereby causing PMOS transistor 102 to turn off. The high voltage at node B causes the voltage at node E to go low, thereby causing the voltage at node C to go high, which in turn, turns on NMOS transistor 104. By turning off one of the transistors off before turning on the other transistor on in output stage 120, referred to also as break-before-make, the crow bar current, i.e., the current from supply voltage Vdd to the ground terminal via transistors 102 and 104 is eliminated thus also preventing ground bounce and power bounce. Resistors 114 and 116 are adapted to reduce overshoot, and allow a soft turn on of the PMOS and NMOS transistors.
One drawback of conventional TTL drivers, such as TTL driver 100 is that because it uses a feedback circuitry, it is not adapted for use in high-speed circuits. The speed limitation is partly due to the following factors. In order for the voltage present on node Vp to go low to turn on PMOS transistor 102, the voltage at node D must go high. Node D has the delay of T1 with respect to node A and defined by the following:T1=Tinv+TRC1+TNOR 
where Tinv is the delay across inverter 124, TRC1 is the RC delay associated with the resistance 116 and the gate capacitance of transistor 104, and TNOR is the delay across NOR gate 112. Therefore, the delay T2 for the signal transition at node A to propagate to node Vp is the following:T2=T1+TRC2+TNANA where TRC2 is the RC delay associated with the resistance 114 and the gate capacitance of transistor 102, and TNAND is the delay across NAND gate 110.
Accordingly, the on and off periods of transistors 102 and 104 occurs roughly in half the period of signal Vin. Therefore, if signal Vin has a frequency of 200 MHz, the on periods of both PMOS transistor 102 and NMOS transistor 104 is roughly 2 nsec. As the window during which output stage 120 may be operative begins to get narrower, TTL driver 100 starts to become less effective thus limiting the speed of TTL driver 100.
FIG. 2 is an exemplary timing diagram associated with TTL driver 100. Before voltage signal Vp make a high-to-low transition 160 to turn on PMOS transistor 102, NMOS transistor 104 is turned off by a high-to-low transition 150 of voltage signal Vn. Similarly, before voltage signal Vn make a low-to-high-to transition 180 to turn on NMOS transistor 104, PMOS transistor 102 is turned off by a low-to-high transition 170 of voltage signal Vp. The increase in the required speed of operation, as well as process and temperature variations may cause delay T2 to become so large as to cause window Twindow defined by transitions 160 and 170 to get narrower and NMOS transistor 104 and PMOS transistor 102 to be on at the same time. As Twindow gets narrower, caused by weakening of the on-state of transistor 102, output driver 102 may not be able to drive the load (not shown), thus disabling output stage 120 from switching and rendering TTL driver 100 ineffective.